tl/f/9965 54act/74act534 octal d flip-flop with tri-state outputs march 1993 54act/74act534 octal d flip-flop with tri-state outputs general description the 'act534 is a high-speed, low-power octal d-type flip- flop featuring separate d-type inputs for each flip-flop and tri-state outputs for bus-oriented applications. a buff- ered clock (cp) and output enable (oe ) are common to all flip-flops. the 'act534 is the same as the 'act374 except that the outputs are inverted. features y i cc and i oz reduced by 50% y edge-triggered d-type inputs y buffered positive edge-triggered clock y tri-state outputs for bus-oriented applications y outputs source/sink 24 ma y 'act534 has ttl-compatible inputs y inverted output version of 'act374 logic symbols tl/f/9965 1 ieee/iec tl/f/9965 2 connection diagrams pin assignment for dip, flatpak and soic tl/f/9965 3 pin assignment for lcc tl/f/9965 4 pin names description d 0 d 7 data inputs cp clock pulse input oe tri-state output enable input o 0 o 7 complementary tri-state outputs tri-state is a registered trademark of national semiconductor corporation. fact tm is a trademark of national semiconductor corporation. c 1995 national semiconductor corporation rrd-b30m75/printed in u. s. a.
functional description the 'act534 consists of eight edge-triggered flip-flops with individual d-type inputs and tri-state complementary outputs. the buffered clock and buffered output enable are common to all flip-flops. the eight flip-flops will store the state of their individual d inputs that meet the setup and hold times requirements on the low-to-high clock (cp) transition. with the output enable (oe ) low, the contents of the eight flip-flops are available at the outputs. when the oe is high, the outputs go to the high impedance state. operation of the oe input does not affect the state of the flip-flops. logic diagram tl/f/9965 5 please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. function table inputs output cp oe d o l lh l l ll h llxo 0 xhx z h e high voltage level l e low voltage level x e immaterial l e low-to-high clock transition z e high impedance o 0 e value stored from previous clock cycle 2
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/distributors for availability and specifications. supply voltage (v cc ) b 0.5v to a 7.0v dc input diode current (i ik ) v i eb 0.5v b 20 ma v i e v cc a 0.5v a 20 ma dc input voltage (v i ) b 0.5v to v cc a 0.5v dc output diode current (i ok ) v o eb 0.5v b 20 ma v o e v cc a 0.5v a 20 ma dc output voltage (v o ) b 0.5v to v cc a 0.5v dc output source or sink current (i o ) g 50 ma dc v cc or ground current per output pin (i cc or i gnd ) g 50 ma storage temperature (t stg ) b 65 cto a 150 c junction temperature (t j ) cdip 175 c pdip 140 c note 1: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. national does not recom- mend operation of fact tm circuits outside databook specifications. recommended operating conditions supply voltage (v cc ) 'act 4.5v to 5.5v input voltage (v i ) 0vtov cc output voltage (v o ) 0vtov cc operating temperature (t a ) 74act b 40 cto a 85 c 54act b 55 cto a 125 c minimum input edge rate ( d v/ d t) 'act devices v in from 0.8v to 2.0v v cc @ 4.5v, 5.5v 125 mv/ns dc characteristics for 'act family devices 74act 54act 74act symbol parameter v cc t a e t a e t a e units conditions (v) a 25 c b 55 cto a 125 c b 40 cto a 85 c typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 2.0 v v out e 0.1v input voltage 5.5 1.5 2.0 2.0 2.0 or v cc b 0.1v v il maximum low level 4.5 1.5 0.8 0.8 0.8 v v out e 0.1v input voltage 5.5 1.5 0.8 0.8 0.8 or v cc b 0.1v v oh minimum high level 4.5 4.49 4.4 4.4 4.4 v i out eb 50 m a output voltage 5.5 5.49 5.4 5.4 5.4 * v in e v il or v ih 4.5 3.86 3.70 3.76 vi oh b 24 ma 5.5 4.86 4.70 4.76 b 24 ma v ol maximum low level 4.5 0.001 0.1 0.1 0.1 v i out e 50 m a output voltage 5.5 0.001 0.1 0.1 0.1 * v in e v il or v ih 4.5 0.36 0.50 0.44 vi ol 24 ma 5.5 0.36 0.50 0.44 24 ma i in maximum input leakage current 5.5 g 0.1 g 1.0 g 1.0 m av i e v cc , gnd i oz maximum tri-state 5.5 g 0.25 g 5.0 g 2.5 m a v i e v il ,v ih current v o e v cc , gnd i cct maximum 5.5 0.6 1.6 1.5 ma v i e v cc b 2.1v i cc /input * all outputs loaded; thresholds on input associated with output under test. 3
dc characteristics for 'act family devices (continued) 74act 54act 74act symbol parameter v cc t a e t a e t a e units conditions (v) a 25 c b 55 cto a 125 c b 40 cto a 85 c typ guaranteed limits i old 2 minimum dynamic 5.5 50 75 ma v old e 1.65v max i ohd output current 5.5 b 50 b 75 ma v ohd e 3.85v min i cc maximum quiescent 5.5 4.0 80.0 40.0 m a v in e v cc supply current or gnd 2 maximum test duration 2.0 ms, one output loaded at a time. note: i cc for 54act @ 25 c is identical to 74act @ 25 c. ac electrical characteristics 74act 54act 74act v cc * t a ea 25 c t a eb 55 ct a eb 40 c symbol parameter (v) c l e 50 pf to a 125 cto a 85 c units c l e 50 pf c l e 50 pf min typ max min max min max f max maximum clock 5.0 100 85 120 mhz frequency t plh propagation delay 5.0 2.5 6.5 11.5 1.5 14.0 2.0 12.5 ns cp to q n t phl propagation delay 5.0 2.0 6.0 10.5 1.5 13.0 2.0 12.0 ns cp to q n t pzh output enable time 5.0 2.5 6.5 12.0 1.5 14.0 2.0 12.5 ns t pzl output enable time 5.0 2.0 6.0 11.0 1.5 13.0 2.0 11.5 ns t phz output disable time 5.0 1.5 7.0 12.5 1.5 14.5 1.0 13.5 ns t plz output disable time 5.0 1.5 5.5 10.5 1.5 11.5 1.0 10.5 ns * voltage range 5.0 is 5.0v g 0.5v ac operating requirements 74act 54act 74act v cc * t a ea 25 c t a eb 55 ct a eb 40 c symbol parameter (v) c l e 50 pf to a 125 cto a 85 c units c l e 50 pf c l e 50 pf typ guaranteed minimum t s setup time, high or low 5.0 1.0 3.5 5.0 4.0 ns d n to cp t h hold time, high or low 5.0 b 1.0 1.0 3.0 1.5 ns d n to cp t w cp pulse width 5.0 2.0 3.5 5.0 3.5 ns high or low * voltage range 5.0 is 5.0v g 0.5v 4
capacitance symbol parameter typ units conditions c in input capacitance 4.5 pf v cc e open c pd power dissipation 40.0 pf v cc e 5.0v capacitance ordering information the device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74act 534 p c qr temperature range family special variations 74act e commercial ttl-compatible x e devices shipped in 13 reels 54act e military ttl-compatible qr e commercial grade device with burn-in device type qb e military grade device with environmental and burn-in package code processing shipped in tubes p e plastic dip d e ceramic dip temperature range f e flatpak c e commercial ( b 40 cto a 85 c) l e leadless ceramic chip carrier (lcc) m e military ( b 55 cto a 125 c) s e small outline (soic) physical dimensions inches (millimeters) 20 terminal ceramic leadless chip carrier (l) ns package number e20a 5
physical dimensions inches (millimeters) (continued) 16 lead ceramic dual-in-line package (d) ns package number j16a 16 lead small outline integrated circuit (s) ns package number m16a 6
physical dimensions inches (millimeters) (continued) 16 lead plastic dual-in-line package (p) ns package number n16e 7
54act/74act534 octal d flip-flop with tri-state outputs physical dimensions inches (millimeters) (continued) 16 lead ceramic flatpak (f) ns package number w16a life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or 2. a critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. national semiconductor national semiconductor national semiconductor national semiconductor national semiconductores national semiconductor corporation gmbh japan ltd. hong kong ltd. do brazil ltda. (australia) pty, ltd. 2900 semiconductor drive livry-gargan-str. 10 sumitomo chemical 13th floor, straight block, rue deputado lacorda franco building 16 p.o. box 58090 d-82256 f 4 urstenfeldbruck engineering center ocean centre, 5 canton rd. 120-3a business park drive santa clara, ca 95052-8090 germany bldg. 7f tsimshatsui, kowloon sao paulo-sp monash business park tel: 1(800) 272-9959 tel: (81-41) 35-0 1-7-1, nakase, mihama-ku hong kong brazil 05418-000 nottinghill, melbourne twx: (910) 339-9240 telex: 527649 chiba-city, tel: (852) 2737-1600 tel: (55-11) 212-5066 victoria 3168 australia fax: (81-41) 35-1 ciba prefecture 261 fax: (852) 2736-9960 telex: 391-1131931 nsbr br tel: (3) 558-9999 tel: (043) 299-2300 fax: (55-11) 212-1181 fax: (3) 558-9998 fax: (043) 299-2500 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications.
|
